1. Field of the Invention
The present invention relates to multicore data processing systems. In a non-limiting application, the present invention relates in particular to multicore systems for a graphical interface based on the use of a graphics processing unit (GPU) which is able to interwork with a central processing unit (CPU). The invention also generally relates to a man-machine interface using such a processing system. In a specific embodiment, the invention relates to data processing systems for man/machine interfaces installed on-board aircraft.
2. Description of the Relevant Art
A need in fact exists to have touch-sensitive man/machine interfaces on-board aircraft.
In the field of graphical interfaces, data processing systems are conventionally used to perform graphics processing operations and create graphical content intended to be displayed on a screen of the interface. This may involve, in particular, creating graphical content comprising manually manipulable touch areas, in this case by a pilot, for the performance of predefined functions.
In the prior art, data processing architectures can generally be implemented in the form of single-core CPUs, multiple central processing units (multi-CPUs) or multicore CPUs. For the implementation of graphics processing, predominantly multicore architectures are used and, in particular, graphics processing units are used that interwork with a central processing unit to increase processing power.
In the case of single-core CPUs, the basic component of an architecture of this type is the processor, which is a component enabling the interpretation of machine instructions defining computer programs.
As is known, in order that a system integrating a processor can operate, it is connected to a permanent storage device which enables the storage of the program that is to be run, to a fast memory for reading and writing the variables used in the running of the programs, and to peripherals of the input/output, communication bus, memory controller, etc., type enabling the exchange of data with the outside of the system.
Modern processors integrated on a chip also integrate a communication bus and very fast cache memory for the storage, as close as possible to the program running area, of the variables used by the program, only the relatively large or least-used variables being sent to the fast memory.
In addition to the processor, Systems on Chip (SoCs) integrate a certain number of peripherals.
Finally, microcontrollers are chips that integrate all of the elements necessary for the operation of the processor, i.e. memory and peripherals.
In the case of single-core CPUs, increasing performance requirements for the processors tend to increase progressively the frequency of operation, made possible by the ever-increasing etching fineness of the silicon. However, the increase in frequency also causes a very substantial increase in consumption, in such a way that the gain in performance becomes marginal in the face of the increase in consumption. It has therefore been proposed to replicate the processing cores in order to parallelize the running of a program, but without increasing the operating frequency.
In a conventional multicore CPU architecture, each core has a first level of cache memory, referred to as the first-level cache memory. The different cores can then share a different cache memory, referred to as the second-level cache memory. A third level of cache memory can be provided when some cores are to be combined.
The parallelization of tasks and the allocation of the instructions to be carried out to one or the other of the cores are performed via the set of instructions interpreted by the processor and by the implemented operating system (OS) which can allocate a given task according to the different cores. This is then referred to as a multicore processor. An implementation strategy of this type may also be applicable to multicore SoCs.
Another strategy consists in providing an architecture similar to the conventional architecture but, instead of parallelizing the operation, the different cores are used to render the processing more reliable. The cores execute the same instructions to within a clock pulse, and the processing operations are then compared in order to obtain a reliable operation under critical conditions. This strategy is known by the name of “Lockstep”.
Another strategy consists in replicating a system rather than a core. This is then referred to as a multiprocessor. Each processor is independent and does not share a cache memory with the others. This type of architecture is generally set up externally in order to implement supercomputers or groups of networked servers to perform relatively complex processing operations requiring substantial processing resources.
In the case of GPU architectures, the graphics processing units, in the same way as CPUs, are processing architectures executing a set of instructions. However, a GPU is a processor optimized for graphics processing operations such as hardware acceleration, three-dimensional processing, video decoding, etc.
GPUs have for a long time consisted of multiple processing cores which distribute graphics tasks among themselves. This involves parallel-processing architectures. As previously indicated, GPUs are predominantly multicore units and may comprise more than 1000 cores, in the case of the most powerful. A certain number of processing operations are allocated to the different cores, to be performed by a controller.
In the case of data processing systems intended to be installed on-board aircraft, as will be understood, this type of electronic system is subject to severe constraints in terms of control of the equipment used, and of determinism, making it necessary to determine with certainty the operation of the system, for example concerning the data transfer duration. They require a validation and certification by the competent authorities. Data processing systems for the on-board man-machine interfaces for commercial aircraft must therefore comply with a certain number of development recommendations and rules.
In the prior art, on-board processing systems are generally implemented on the basis of “Commercial Off The Shelf” (COTS) components, i.e. components that are mass-produced in order to reduce production and maintenance costs. However, the use of conventional COTS components firstly causes problems of obsolescence, making it necessary to procure a large number of components and store them in order to guarantee the maintainability of the product. Given the development time and service life of a product for the aeronautical industry, which may amount to several decades, it is often the case that the components used in the design of an electronic system are in fact obsolete even before the end of the design process, making it necessary to implement periodic modification and recertification phases.
Secondly, the COTS electronic components are generally derived from consumer markets or from the telecommunications sector and are then optimized for non-aeronautical applications. Their use in the aeronautical field involves the deactivation of the original applications, their modification to make them compatible with the aeronautical field, then a certification, incurring additional costs.
Furthermore, standard multicore processing systems comprise only peripheral systems and memories shared among the different processing cores. The cores communicate with data input and output interfaces via a common interface bus to access resources shared between the cores. This results in a requirement for arbitration in the potentially concurrent access to said peripheral systems. This concurrent access is managed in a conventional COTS system by an uncontrolled coherence system. The use of COTS components in an aeronautical system therefore requires the implementation of a large number of software and hardware locks to guarantee the operation of the components while following the recommendations of the certification authorities. The addition of these locks entails a substantial degradation in the performance of the central data processing units.